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Ric2's avatar
Ric2
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2 years ago

Deadlock while filling pipe for simulation

Hi, following best practice as descibed here we run into trouble with stalled writes. When you create a testbench for a oneAPI kernel that you intend to compile as an IP core, write all your data...
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Kevin_Xu_Intel's avatar
Kevin_Xu_Intel
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2 years ago

Hi Ric,

I have simulated you reproducer a several times, here are what i found:

  1. I see your issue number (1) where when a non-blocking pipe write is writing into a pipe that has hit the implicit capacity, the write failed signal isn't being raised. I will ask around if this is a known behaviors.
  2. I don't really see issue (2). The data seems to be processed in burst for me (about every ~17000) but it eventually reach the end (see the output). The simulation dose took about 1 hour with ModelSim pro. So if you are simulating with a starter edition, it is going to take very long time to simulate (may appears to be stalled).
  3. "vsimk: src/hls_cosim_ipc_socket.cpp:133: virtual void IPCSocket::send(const void*, int): Assertion `0 && "send() failed"' failed" I believe this is the expected error when stopping simulation with ctrl+C.

Simulation output (only shown the begining and the end)

Running on device: SimulatorDevice : Multi-process Simulator (aclmsim0)
WR ... Input: 0	 Output: 0	 Diff: 0
RD STALL WORKS! 

WR ... Input: 1000	 Output: 0	 Diff: 1000
RD ... Input: 1274	 Output: 0	 Diff: 1274
WR ... Input: 2000	 Output: 41	 Diff: 1959
WR ... Input: 3000	 Output: 99	 Diff: 2901
WR ... Input: 4000	 Output: 156	 Diff: 3844
WR ... Input: 5000	 Output: 222	 Diff: 4778
WR ... Input: 6000	 Output: 292	 Diff: 5708
WR ... Input: 7000	 Output: 366	 Diff: 6634
WR ... Input: 8000	 Output: 438	 Diff: 7562
WR ... Input: 9000	 Output: 513	 Diff: 8487
WR ... Input: 10000	 Output: 588	 Diff: 9412
WR ... Input: 11000	 Output: 662	 Diff: 10338
WR ... Input: 12000	 Output: 735	 Diff: 11265
WR ... Input: 13000	 Output: 809	 Diff: 12191
WR ... Input: 14000	 Output: 882	 Diff: 13118
WR ... Input: 15000	 Output: 955	 Diff: 14045
RD ... Input: 15623	 Output: 1000	 Diff: 14623
WR ... Input: 16000	 Output: 1029	 Diff: 14971
WR ... Input: 17000	 Output: 1097	 Diff: 15903
WR ... Input: 18000	 Output: 1159	 Diff: 16841

... ...

WR ... Input: 982000	 Output: 952124	 Diff: 29876
RD ... Input: 982875	 Output: 953000	 Diff: 29875
WR ... Input: 983000	 Output: 953126	 Diff: 29874
RD ... Input: 983859	 Output: 954000	 Diff: 29859
WR ... Input: 984000	 Output: 954142	 Diff: 29858
RD ... Input: 984858	 Output: 955000	 Diff: 29858
WR ... Input: 985000	 Output: 955143	 Diff: 29857
RD ... Input: 985857	 Output: 956000	 Diff: 29857
WR ... Input: 986000	 Output: 956147	 Diff: 29853
RD ... Input: 986853	 Output: 957000	 Diff: 29853
WR ... Input: 987000	 Output: 957148	 Diff: 29852
RD ... Input: 987852	 Output: 958000	 Diff: 29852
WR ... Input: 988000	 Output: 958149	 Diff: 29851
RD ... Input: 988852	 Output: 959000	 Diff: 29852
WR ... Input: 989000	 Output: 959150	 Diff: 29849
RD ... Input: 989835	 Output: 960000	 Diff: 29835
WR ... Input: 990000	 Output: 960166	 Diff: 29834
RD ... Input: 990822	 Output: 961000	 Diff: 29822
WR ... Input: 991000	 Output: 961178	 Diff: 29822
RD ... Input: 991823	 Output: 962000	 Diff: 29823
WR ... Input: 992000	 Output: 962178	 Diff: 29822
RD ... Input: 992823	 Output: 963000	 Diff: 29823
WR ... Input: 993000	 Output: 963179	 Diff: 29821
RD ... Input: 993823	 Output: 964000	 Diff: 29823
WR ... Input: 994000	 Output: 964177	 Diff: 29823
RD ... Input: 994822	 Output: 965000	 Diff: 29822
WR ... Input: 995000	 Output: 965179	 Diff: 29821
RD ... Input: 995810	 Output: 966000	 Diff: 29810
WR ... Input: 996000	 Output: 966199	 Diff: 29801
RD ... Input: 996802	 Output: 967000	 Diff: 29802
WR ... Input: 997000	 Output: 967198	 Diff: 29802
RD ... Input: 997804	 Output: 968000	 Diff: 29804
WR ... Input: 998000	 Output: 968197	 Diff: 29803
RD ... Input: 998804	 Output: 969000	 Diff: 29804
WR ... Input: 999000	 Output: 969197	 Diff: 29803
RD ... Input: 999807	 Output: 970000	 Diff: 29807
Input Done!
RD ... Input: 1000000	 Output: 971000	 Diff: 29000
RD ... Input: 1000000	 Output: 972000	 Diff: 28000
RD ... Input: 1000000	 Output: 973000	 Diff: 27000
RD ... Input: 1000000	 Output: 974000	 Diff: 26000
RD ... Input: 1000000	 Output: 975000	 Diff: 25000
RD ... Input: 1000000	 Output: 976000	 Diff: 24000
RD ... Input: 1000000	 Output: 977000	 Diff: 23000
RD ... Input: 1000000	 Output: 978000	 Diff: 22000
RD ... Input: 1000000	 Output: 979000	 Diff: 21000
RD ... Input: 1000000	 Output: 980000	 Diff: 20000
RD ... Input: 1000000	 Output: 981000	 Diff: 19000
RD ... Input: 1000000	 Output: 982000	 Diff: 18000
RD ... Input: 1000000	 Output: 983000	 Diff: 17000
RD ... Input: 1000000	 Output: 984000	 Diff: 16000
RD ... Input: 1000000	 Output: 985000	 Diff: 15000
RD ... Input: 1000000	 Output: 986000	 Diff: 14000
RD ... Input: 1000000	 Output: 987000	 Diff: 13000
RD ... Input: 1000000	 Output: 988000	 Diff: 12000
RD ... Input: 1000000	 Output: 989000	 Diff: 11000
RD ... Input: 1000000	 Output: 990000	 Diff: 10000
RD ... Input: 1000000	 Output: 991000	 Diff: 9000
RD ... Input: 1000000	 Output: 992000	 Diff: 8000
RD ... Input: 1000000	 Output: 993000	 Diff: 7000
RD ... Input: 1000000	 Output: 994000	 Diff: 6000
RD ... Input: 1000000	 Output: 995000	 Diff: 5000
RD ... Input: 1000000	 Output: 996000	 Diff: 4000
RD ... Input: 1000000	 Output: 997000	 Diff: 3000
RD ... Input: 1000000	 Output: 998000	 Diff: 2000
RD ... Input: 1000000	 Output: 999000	 Diff: 1000
Output Done!
FAILED