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Ric2's avatar
Ric2
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2 years ago

Deadlock while filling pipe for simulation

Hi, following best practice as descibed here we run into trouble with stalled writes. When you create a testbench for a oneAPI kernel that you intend to compile as an IP core, write all your data...
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Kevin_Xu_Intel's avatar
Kevin_Xu_Intel
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2 years ago

Hi Ric,

I did some testing, it dose looks like in emulation, a non-blocking read of a empty pipe causes crash. I will look into this problem.

Dose the crash happens to you in simulation? I was not able to reproduce the crash in simulation.

Thanks,

-Kevin

  • Ric2's avatar
    Ric2
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    2 years ago

    Hi Kevin,

    I guess there are race conditions. I sporadically see issues in simulation too:

    .../build$ ./streaming.fpga_sim
Running on device: SimulatorDevice : Multi-process Simulator (aclmsim0)
terminate called after throwing an instance of 'sycl::_V1::runtime_error'
  what():  Enqueue process failed. -59 (PI_ERROR_INVALID_OPERATION)
Aborted (core dumped)

    Please check the host pipe write command in your code. Modify the core to not accept data at it's input for a longer time (backpressure condition). Then the host will throw an error when the pipe is full but the host write is not handling this properly.

    To reproduce, just modify line 57:

    57   // while (!end_of_packet) {
57    while (end_of_packet) {
58      // Read in next pixel

    As the reproducer is a bit of artificial, I see this issue in our production design too.

    I hope this helps you to find the root cause of these problems!

    Regards, Ric.