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Lily1234's avatar
Lily1234
Icon for New Contributor rankNew Contributor
5 years ago
Solved

Cyclone10 GX SERDES using

Hi, My project need to generate a 16 bit (@1.28Gbp/s data rate) uers data. So I use Serdes to achieve this function. Feed one pair 40M reference to IO/PLL and config SerDes in TX mode. For the ...
  • Ash_R_Altera's avatar
    Ash_R_Altera
    5 years ago

    Hi,


    Below could be the reasons for this error:

    1) When using dedicated SERDES circuitry, it does not support differential SSTL IO standard. The SERDES requires a direct connection to I/O and hence it can only interface to true LVDS I/O. So, please change IO standard of TX pins to LVDS.

    2) Check the reference clock connection. It can be either from the same bank or an adjacent bank.


    Regards.




Ash_R_Altera's avatar
Ash_R_Altera
Icon for Regular Contributor rankRegular Contributor
5 years ago

Hi,


Below could be the reasons for this error:

1) When using dedicated SERDES circuitry, it does not support differential SSTL IO standard. The SERDES requires a direct connection to I/O and hence it can only interface to true LVDS I/O. So, please change IO standard of TX pins to LVDS.

2) Check the reference clock connection. It can be either from the same bank or an adjacent bank.


Regards.




  • Lily1234's avatar
    Lily1234
    Icon for New Contributor rankNew Contributor
    5 years ago

    Hi,

    Thanks for your kindly reply. When I change the I/O standard from SSTL to LVDS, the compilation succeeds. And I use pin H1/G1 (bank 3B) as reference clock.

    But I still feel vey confused, I double check the IO standard in handbook. It shows SERDES supports SSTL.

    Could you please explain more which occasion we can use LVDS and which occasion use differential SSTL-1.2V?

    Below is the handbook link.(https://www.intel.com/content/www/us/en/programmable/documentation/vua1487061384661.html#prw1491785518129)

    Thanks very much!

    Best regards,

    Lily