Forum Discussion

LennartVH's avatar
LennartVH
Icon for New Contributor rankNew Contributor
3 years ago

CRAM SEU detection and mitigation support with OpenCL/oneAPI

Hi there, I'm doing a large and long-running FPGA supercomputing project, with an average of 20 FPGAs running in parallel over the course of 5 months. Our project is very sensitive to cosmic ...
BoonBengT_Altera's avatar
BoonBengT_Altera
Icon for Moderator rankModerator
3 years ago

Hi LennartVH,


Thank you for posting in Intel community forum and hope all is well.

Mind if I ask what are the device used from you end?

Also is the CRAM mention part of the built in of the device or separate connected?


Per my understanding the ECC are not built in on openCL/oneAPI, allow me to confirm on that.

And as for the code snippet mention in which header files did you found it?

Hope to hear from you soon.


Best Wishes

BB


  • LennartVH's avatar
    LennartVH
    Icon for New Contributor rankNew Contributor
    3 years ago

    Hi again BoonBengT, Thank you for responding.

    My apologies, I should have specified my hardware. I'm working on the Intel Stratix 10 GX 2800 on a Bittware N520 board. There are two types of errors I think are the most prevalent/important: (If I'm leaving out an important class please let me know)
    - M20K errors, These are handled through built-in ECC in the M20K blocks. I handle these myself.
    - Configuration RAM errors, aka errors in the FPGA fabric configuration. These are the ones I wish to detect. Intel documentation indicates that there should be dedicated hardware for automatic scanning. This hardware then drives the CRC_ERROR pin as I understand it.

    I've looked in bittware's documentation, and confirmed that this BSP does handle the CRC_ERROR pin. The generated aoc quartus project also has the periodic integrity checking flag enabled.


    I couldn't find it mentioned anywhere in the documentation though. What the documentation does mention is the -ecc flag (https://www.intel.com/content/www/us/en/docs/programmable/683846/21-4/compiling-your-kernel-with-memory-error.html) , which adds M20K error detection in OpenCL code, but does not mention CRAM error detection.

    I was able to find the above function in the intel header files at:
    .../intelFPGA_pro/21.4.0/hld/host/include/CL/cl_ext_intelfpga.h

    I think this is called when the CRC_ERROR pin is signaled. But I don't exactly know how this callback behaves. You can see that testing this function is not exactly trivial. (I don't think they'll let me into the data center with a gamma-ray cannon )

    If you have any documentation or info on this, then please let me know. I can't afford even a single undetected error in this project.

    Kind regards,
    Lennart