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derSpieler's avatar
derSpieler
Icon for New Contributor rankNew Contributor
5 years ago

Component Done signal remains asserted in FPGA, not in Simulation

Hello, I have created a component in HLS which should take a 1280 bit signal (passed by value), and should stream it out in 20 packets of 64-bit each. The task is simple, and both the simulation ...
AnilErinch_A_Intel's avatar
AnilErinch_A_Intel
Icon for Frequent Contributor rankFrequent Contributor
5 years ago

Hi ,

Can you share the signal tap waveforms for the 3 packets scenario and hanging scenario.

Also can you please let us know the status of the stall signal when the component hangs.

Thanks and Regards

Anil