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TLeng2's avatar
TLeng2
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6 years ago

Arria 10 Dev Kit, adjust OpenCL BSP a10soc2ddr to use only the FPGA Memory..

I have a A10 Board with 2GB Memory for the HPS and 4GB Memory attached to the emif side of the FPGA, I want to get the Opencl system up and running without the shared memory stuff. ( boardtest.cl for...
Douglas_P_Intel's avatar
Douglas_P_Intel
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6 years ago

Did you delete all the components in red? (You have to modify the HPS component to remove the SDRAM0 and SDRAM1 bridges)

Did you delete the following from the board_spec.xml file?

<interface name="board" port="kernel_mem1" type="slave" width="512" maxburst="16" latency="240" address="0x40000000" size="0x40000000"/>

This statement creates the AVMM Master on the left. The clock bridge on the left should have a port kernel_mem1.

Make sure the rebuild the drivers AND the utilities (like diagnose) after making hardware changes.