AI Suite - Streaming from HPS to DLA IP

Hi Mads_From_Denmark 

Regarding your question on FPGA AI Suite, unfortunately the create hps image script is hardcoded to support only the official Agilex 5, 7 and Arria10 devkit only, thus it will not support DE25-NANO as the hardware is different even though it is based on Agilex5.

Changing the script might be a hassle as you have rewrite yocto recipes, change the configuration for uboot DTS, and edit the changes to suit DE25.

FYI SOC embedded development suite have been discontinued for some time already. https://www.rocketboards.org/foswiki/Documentation/SoCEDS

Instead , I think you could try doing this

1) Start with the Terasic Linux BSP

- reuse what Terasic have for your board

You can refer to this Agilex 5 SoC Golden System Reference Design (GSRD)  (https://altera-fpga.github.io/rel-24.1/embedded-designs/agilex-5/e-series/premium/gsrd/ug-gsrd-agx5e-premium/#gsrd-overview)

It contains the steps to enable Linux on Agilex 5 devkit. While it uses the official Dev Kits as examples, the steps also applies to your DE25 board, just you need to change certain configuration to make it work (change the device tree uboot/linux to use DE25 instead of devkit, modify the GSRD , by right Terasic should have all these example ready for you).

The  GSRD covers the fundamental boot ingof Agilex 5 (Boot ROM, U-Boot, ATFF, Linux), how to compile the Linux kernel, and how the HPS communicates with the FPGA fabric.

2)  Reuse the DE25 GSRD design and instantiate your HPS and DLA IP in Platform Designer and assign your memory-mapped addresses (you can refer to the GSRD for Agilex5 AI Suite example to do the porting). Use the DE25 DTS and edit it to include the DLA IP to the kernel including the base address and IRQS that is based on Platform Designer. Then compile it following the Devkit guide.

Take note that we have never verified the CoreDLA design outside of those indicated devkit 

Thanks

Regards

Kian