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BXia's avatar
BXia
Icon for Occasional Contributor rankOccasional Contributor
4 years ago

Agilex FPGA Quartus project simulation issue

To whom it may concern, 我们在仿真基于Agilex FPGA的工程时，发现mac的link比别的开发板（基于Stratix 10 FPGA）慢了很多，agilex的mac大概需要48wns才能link上，而Stratix 10 FPGA的mac大概只需要15wns就能link上。 我们分析的原因是，agilex生成的ip core（phy_10g_etile）里p...
paveetirrasrie_Altera's avatar
paveetirrasrie_Altera
Icon for Frequent Contributor rankFrequent Contributor
4 years ago

Hi,


After having discussion with my teammates, looks like there will be different in simulation model in different devices.

So I don't think there's any specific way to shorten the timing for linking as it depends on simulation models.


Regards,

Pavee