Forum Discussion
Agilex 5 Precision DSP block simulations
- 1 year ago
Hi,
Thank you for looking into this further.
I agree the Adder is correct and i've also now seen correct behavior, so i'm not sure why it appeared incorrect previously.
Regarding the MAC; i still see an issue and there has now been an IPS case opened for it (via our AE).
Since there is an IPS case open i'm happy to mark this particular query as closed.
Thank you again for your support,
Simon
Hi,
Since you're currently unable to provide a simulation test case, I’ve created a simple test using the fp32_add function from the Native Floating Point DSP IP for Intel Agilex FPGA. The simulation was performed using Quartus 24.3 targeting an Agilex 5 device, and it appears to run successfully, as shown in the attached screenshot.
I’ve shared the simulation folder (fp_add_dsp.zip) via email for your reference. You can review the following files to rebuild the simulation on your end:
/sim/mentor/msim_setup.tcl
/sim/fp_add_dsp.v
tb_fp_add_dsp.v
Please let me know if you have any questions or need further assistance. Thank you.
- CheepinC_altera1 year ago
Regular Contributor
Hi,
Just to keep you informed — I’ve tested the Native Floating Point DSP IP in MAC mode, and the simulation appears to run correctly (please ignore the last 3 signals which are irrelevant).
Given the discrepancies in our observations, please feel free to share your simulation files that replicate the issue you're seeing. This will help me investigate further and identify any potential differences or root causes.
Let me know if you have any questions or need additional support. Thank you.
Best regards,
Chee Pin