Forum Discussion
New ContributorAgilex 5 Precision DSP block simulations
Hi,
Thank you for looking into this further.
I agree the Adder is correct and i've also now seen correct behavior, so i'm not sure why it appeared incorrect previously.
Regarding the MAC; i still see an issue and there has now been an IPS case opened for it (via our AE).
Since there is an IPS case open i'm happy to mark this particular query as closed.
Thank you again for your support,
Simon
Regular ContributorHi,
Just would like to follow up with you on this. Please let me know if there is any concern. Thank you.
New ContributorHi,
To replicate the behavior with the Adder, simply create a wrapper around it and try and Add two number together - you'll see the simulation fails and the output simply tracks one of the inputs.
It's a bit more involved with the MAC, although if you run a simulation with it doing multiple MAC and then de-assert the accumulate signal every 5 cycles you'll notice the outputs do not match what you'd expect. By that i mean they do not match what i get from Python or from running the same testbench on hardware.
It's tricky getting test cases to you at this time as i don't have the spare time required to put something together and package it all up etc. Do you know of nay issues with the simulation models? Are there any later versions available ?
Many thanks,
Simon
- S_J_S
By the way; is it worth me posting this question in other categories? I find the listed categories do not really match what my question relates to so it's hard to know if this is the correct one.
