Forum Discussion
It looks like you have some mismatched tools installed. You don't need the FPGA SDK for OpenCL; here is what you need (from our homepage
- oneAPI DPC++ base toolkit 2024.2
- FPGA support Package 2024.2 (the FPGA compiler is no longer distributed with the base toolkit since 2024.2)
- Quartus Prime 21.2 (with Agilex 7 Device support)
- BSP for DE10-Agilex card
For best results, use one of the FPGA code samples, as those are the ones we regression test:
Thanks for your advice. With the FPGA support package I can now
compile SYCL code for FPGA targets. It seems aoc (from the FPGA
support package) uses the correct BSP:
$ aoc -list-boards Board list: B1E1_8GBx4 Board Package: /vol/opt/intelFPGA_pro/21.2/hld/board/de10_agilex B2E2_8GBx4 (default) Board Package: /vol/opt/intelFPGA_pro/21.2/hld/board/de10_agilex ...
I create a pre-synthesis report from the FGPA vector_add example like this:
$ icpx -v -fsycl -fintelfpga -Xshardware -Xstarget=Agilex7 -fsycl-link=early vector_add.cpp -o reportz
When I open the report it says "Report has invalid data. Ok to
proceed?" If I do so I get a report that is not quite right. In
particular, the global memory bandwidth estimates are wrong (see
screenshot). Is there something else I need to do? Like add something
to the icpx command to get it to use the right BSP?