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Dhilip's avatar
Dhilip
Icon for New Contributor rankNew Contributor
3 years ago

10M08SAU324I7G SMAP Length Routing constraints

Hi ,

We are using 10M08SAU324I7G chipset in our design. We are using SMAP interface to Program the FPGA(XCKU5P series) from CPLD.

Below are the Pins are used for SMAP interface. In our design, we have routed 15inch traces between FPGA and CPLD due to dense board. For this we have simulated and it pass only "18_RIO_R50C" model.

Is it possible to configure this "18 RIO R50C" model for the pins listed below?Please advise and share if any guidelines.

2 Replies

  • Farabi's avatar
    Farabi
    Icon for Regular Contributor rankRegular Contributor
    3 years ago

    Hello,


    I’m glad that your question has been addressed, I now transition this thread to community support. If you have a new question, feel free to open a new thread to get the support from Intel experts. Otherwise, the community users will continue to help you on this thread. Thank you.


    rgards,

    Farabi