Most RecentWhat assignments do I need for a PCIe Gen1, Gen2 or Gen3 design that targets an Arria 10 ES2, ES3 or production device?Mentor Graphics AXI Verification IP AE in the Quartus II 13.1 release does not support QuestaSim 10.2b for windowsAre there any problems with version 13.1 of the JNEye tool when modelling the receiver of Arria 10 GX/T devices?Why do I see random read errors when using the ALTDQ_DQS2 megafunction?Why doesn't the Soft IP PCIe* core send my Avalon®-MM memory read request to PCIe* bus?Is there a known issue with the scandata port when using the ALTPLL_RECONFIG megafunction in the Quartus® II software version 13.1?Why do I get an error message when compiling my design targeting Arria V Hard IP for PCI Express in Quartus II software versions 11.1 and 11.1 SP1?How do you display only the leaf name instead of the full path signal name in the ModelSim-Altera wave window?Internal Error: Sub-system: VPR20KMAIN, File: /quartus/fitter/vpr20k/quartus_interface/ qi_common/vpr_qi_high_speed_low_power_tiles.cpp, Line: 5985Error (292019): Core Nios II Processor (6AF7_00A2) is not enabled for current device family
