Most RecentWhy does OpenCL compiler generates synthesis errors related to Port mismatch while customizing OpenCL Board Support package for Arria10?Warning: Please use -profile instead of --profileError: Could not find fit report afu_opencl_kernel.fit.rpt under compile directoryUnable to unlock /intelFPGA_pro/17.1.1/hld/installed_packagesWhy does applying the merge attribute to an array declared within an unrolled or partially unrolled loop create an unexpectedly wide memory using Intel® FPGA SDK for OpenCL version 19.1?Why do I get bad performance when compiling vector add example design with Intel® FPGA SDK for OpenCL™?ERROR: UNRECOGNIZED ERROR CODE (-1001), Location: ../common/src/AOCLUtils/opencl.cpp:297, Query for number of platforms failedWhy does the --seed argument not get passed when performing a flat or base compile using the Intel® FPGA SDK for OpenCL™ flow?Why do I see the hold timing violation in DCP1.2 OpenCL BSP design?Why does area estimation may present difference between text output and report.html with FPGA OpenCL™ SDK?
