Why do I see the hold timing violation in DCP1.2 OpenCL BSP design?

Description

You may see a small hold timing violation when you compile a DCP1.2 OpenCL BSP design.

Resolution

This hold timing violation does not cause any functional issue on DCP1.2 OpenCL BSP design.

This problem has been fixed in DCP 1.2.1 OpenCL BSP design.