Most RecentWhy are ECC error flags observed when testing the Interlaken (2nd Generation) Intel® FPGA IP core on hardware?Why did Agilex™ 7 devices fail to recover after I accidentally programmed the wrong encryption key?Why aren't msb_aOctetsTransmittedOK or msb_aOctetsReceivedOK statistics registers of Triple-Speed Ethernet IP Core incremented?Internal Error: Sub-system: PTI, File: /quartus/tsm/pti/pti_re_tree_annotator.cpp, Line: 2086Why does the compilation time increases when global Advanced I/O Timing settings are used for the Stratix® 10 devices?Why are there timing violations on the *pld_fpll_shared_direct_async_out_hioint[2] clock domains within the Agilex™ 7 device F-Tile PMA/FEC Direct PHY Multirate FPGA IP?Are the default XAUI PHY IP transceiver PMA settings in Quartus II Software Version 10.1-SP1 and earlier capable of implementing a XAUI compliant link in Stratix IV GX and GT devices?Arria V Hard IP for PCI Express IP Core VOD Too LowWhy do I see "Error(18108): Can't place multiple pins assigned to pin location" in my design with Partial Reconfiguration?Transceivers are not preserved when the device remains powered and unprogrammed for an extended period of time.
