Most RecentInternal Error: Sub-system: HSSI, File: /quartus/periph/hssi/hssi_reconfig_op.cpp, Line: 5331Are there any known issues with the Parallel Flash Loader (PFL) in the Quartus II software version 12.1SP1 when data is read from an EPCQ or Micron QSPI flash device?Internal Error: Sub-system: CDB_SGATE, File: /quartus/db/cdb_sgate/cdb_sgate_wys_sweep.cpp, Line: 3994Unable to lock chain <Hardware disabled>Why does the GMII channel fail when using the CPRI webcore IP on the Intel® Stratix® 10 E-tile devices?Why do I get the following error during the Quartus® II Analysis & Synthesis when upgrading an Avalon-MM Stratix V Hard IP for PCI Express IP core design from version 12.1 to v13.0?When using the E-tile Hard IP for Ethernet Intel® FPGA IP in 10G/25G mode, why are malformed packets detected after assertion of the o_sl_tx_lanes_stable signal?Why does my RTL inferred RAM use more registers in the Quartus II software version 13.1 than in previous versions?Why do I see recovery timing violations within the ALTLVDS_RX megafunction in my design?Warning (11106): Shared VREF is used as GPIO <pin name>. This action reduces fmax performance.
