Warning (11106): Shared VREF is used as GPIO <pin name&gt. This action reduces fmax performance.

Description

VREF pins have a high pin capacitance than other pins in devices that support dual-purpose VREF pins. Avoid using the VREF pins as an I/O pin of a bus or clock function because the higher capacitance will slow the edge rates and affect I/O timing.

Resolution

Is there a longer delay on VREF pins when used as I/O compared to general purpose I/O pins in Cyclone-series devices that support dual-purpose VREF pins?

Updated 1 month ago

Version 3.0

arria® v fpgas and socs

troubleshooting

Knowledge Base Article

Warning (11106): Shared VREF is used as GPIO <pin name&gt. This action reduces fmax performance.

Description

Resolution

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