Why do I see recovery timing violations within the ALTLVDS_RX megafunction in my design?

Description

You may see recovery timing violations on the reset path from your user-coded reset register through the rx_cda_reset port of the ALTLVDS_RX megafunction to the following signals *altlvds_rx_component|*auto_generated|rx*bit_slip_reg

Address these paths by applying a set of set_multicycle_path assignments such as the ones below:

set_multicycle_path -from [get_keepers <name of source node>] \
    -to [get_keepers {*altlvds_rx_component|*auto_generated|rx*bit_slip_reg}] \
    -setup -end 3 .
set_multicycle_path -from [get_keepers <name of source node>] \
    -to [get_keepers {*altlvds_rx_component|*auto_generated|rx*bit_slip_reg}] \
    -hold -end 2 .


The values of these assignments may vary depending on the relationship between the clock used for your external register and the rx_outclock port of the ALTLVDS_RX megafunction.

Altera recommends using the rx_outclock port of the ALTLVDS_RX megafunction to clock the external reset register to synchronize the reset to the correct domain.