Most RecentWhat are the active bit mappings of the Native PHY rx_parallel_data and tx_parallel_data busses when the "Enable simplified data interface" is disabled for Stratix V, Arria V, and Cyclone V transceiver devices?Why is the number of DSP block 9-bit elements shown as "N/A until Partition Merge" even after the design is fully compiled?How do I change the clock frequency of the USB-Blaster II download cable?Why are IBIS models not generated for the PCI IO standard by the Intel® Quartus® II design software when the current strength is set to a minimum?Why does the F-Tile 25G Ethernet FPGA IP fail to send Remote Fault patterns on Tx when the Rx is in a reset or unlock state?Why does "fixedclk_locked" signal keep low when "Enable Configuration via the PCIe link" parameter in MegaWizard window of PCIe is enabled?Why can't I meet the target impedance when entering 0mA into the PDN Tool?Why can I not export interfaces with the Clipper VIP Suite block in Qsys?Why does the rx_latency_adj_10g and tx_latency_adj_10g signal descriptions refer to 1g for the Arria V and Stratix V devices in the Altera Transceiver PHY IP User Guide?Center PLL in Arria V Cannot Drive Two Independent PHY Clock Networks
