Why does the F-Tile 25G Ethernet FPGA IP fail to send Remote Fault patterns on Tx when the Rx is in a reset or unlock state?

Description

This is expected behavior in F-Tile 25G Ethernet FPGA IP. Users must access the LINK_FAULT register at address 0x405, forcing the Tx to send Remote Fault patterns while Rx is in a reset or unlock state.

Resolution

There is no plan to change this IP behaviour.

User logic must perform extra control if required to set Force Remote Fault bit[3] of the LINK_FAULT register to let the link partner know the status.