Most RecentAre there any good debugging tools that can help us troubleshoot easily?How to assign a dual-region clock network in assignment editor?'Custom PHY v17.1' IP in Platform DesignerI can not post a question after I log in to this forum using Microsoft Edge but if I use Google Chrome (as I'm dong here) it works fine. Within Edge just clicking on the "Ask A Question" button does nothing!Configuring the Quartus IP library "RS232 UART, CLK signalIt is strange to me that the verilog program behave differently when I turn a register variable into an output register variable.Quartus v18.0.1 Avalon Verification IP Suite Update?Can't run the version of modelsim packaged with Quartus 18.0Problem simulating Verilog ip catalog uart with my VHDL design using Modelsim Altera starter editionDDR3 burst size
