Most Recentwhy rx_is_lockedtodata is not set to 1 after the work of the controller?I am trying to create a Viterbi IP block and use in my Arria V GZ design. I am not running an Avalon bus internal. I see that when I choose the Viterbi IP from the DSP/Error Detection and Correction section, it is generated using Qsys.Where can i get Quartus Programmer software v14 for 32 Bit?I have downloaded HDLC IP from opencores which is having front side bus as wishbone, I am using CYCLONE 4 FPGA with NIOS II processor. I want to interface HDLC IP to NIOS processor(AVALON BUS) please explain how to interface.is there any option to change the data width of Avalon interface in ddr3 controller?PFL Devices SupportDoes an ATX PLL configured as a Clock Buffer need a reference clock of it's own or can the pll_refclk0 port be tied to ground?JESD204B IP Core and variable sampling clock?Several Word align patternsjesd204b block works on a project, but fails when the top level heirarchy is being exported and used in another similar project
