Most RecentHi, I'm trying to make a delay instruction in verilog, I have an output (PWM) and I want to generate another output (PWM1) from PWM but with a delay: i tried this : assign #50 pwm1 = pwm; but it's not working best regards,Triple Speed Ethernet IP - 1000BASE-X/SGMII PCS only - word alignment included?Phase relationships for External PLL signals with the LVDS SERDES Receiver IP coreDoes Generic QUAD SPI controller II support EPCQ-A devicesFFT IP MATLAB C-model seems not bit trueCordic/DividerSeriallite ii IP works in full duplex, stream mode. Although stat_rr_link is low, the data can still be received correctly. Whether or not in this mode, the connection is established independently of the indication of the pinI need the Reliability Report for the 5CEFA5F23C7N Cyclone V FPGA."Error 16301 IOPP reference clock is not connected to a clock pin" when trying to use a PLL clock output for EMIF on Arria 10 devicemy PLL does not set "pll_locked" to 1 when I lower "pll_powerdown" to 0. The flag "PLL Auto Reset" is set in the IP core
