Phase relationships for External PLL signals with the LVDS SERDES Receiver IP core

Hello,

I am using the LVDS SERDES Receiver IP core on a Cyclone V. I'm using an external PLL and am trying to understand how to adjust the phase relationships for clock and data inputs that are not edge aligned. I am confused by Figure 9. of the LVDS SERDES IP Core User guide (attached below). Specifically, I don't see how the diagram for c1 shows a phase shift of positive 288 degrees. If, as suggested by c2, a phase shift of –18 degrees corresponds to a right shift of the rising edge by 5% of a cycle, then 288 degrees should correspond to a left shift of the rising edge by 80% of a cycle, which is not what is shown by the figure.

Interestingly, Figure 17. of the LVDS SERDES IP Core User Guide for the Arria 10 and Cyclone 10 (also attached below) is a very similar diagram: the phase relationships between the output clocks are the same as in the first diagram, but the labeled phase shifts are different. This figure makes sense to me, as +18 degrees corresponds to a right shift of 5% of a cycle and 324 degrees corresponds to a right shift of 90% of a cycle.

I would appreciate if someone could help me resolve my confusion here. Is Figure 9. inconsistent, or am I fundamentally misunderstanding something?

Thanks!