Most RecentI have this problem: https://www.intel.com/content/www/us/en/programmable/support/support-resources/knowledge-base/solutions/fb293743.html Is there a solution? Thanks a lot for your replyDCFIFO Megafunction simulation problemProblem with EPCQ-L1024 extended QUAD input fast transferWriting to control and status register from the code and from system console scriptsJESD204B TX ipcore使用问题！How can I change Input Pins Default Value?I use the FPGA of cyclone V which type is 5CGXFC3B7F23C8N ,which has 1 GXB Bank （3 transceiver channel）,CH0/CH1/CH2，but CH1 has errorHow to use Avalon Bus by Eclipse?Random Number Generator IP for Quartus 18.0 and higherWhat will happen if I generated a FIFO using the IP but I tied the ACLR and SCLR to '0' (i.e. I don't have a ALCT or SCLR signal input) ?? Will it still work??
