Most RecentJesd204b interface seems to misbehave after upgrading quartus from 16 to 19C10 GX FPll ReconfigError (11666): Device "5CSEBA6U23I7" does not support "Channel PLL"FFT IP core sink_ready never gets assertedImplementation of a PCIe root port on stratix 10 MX devkit.Why is the FFT IP buffered burst not producing correct source_sop/eop/valid but still produces source_real/imag?EP4CE22F17C8N Dimension details required to draw the decalWhat is the best way to generate a multi-port front end using the EMIF for a Cyclone 10 GX device?I am using cyclone III FPGA with Quartus 10.0 spl software. In my design I am using ALTFP-DIV ( 32-bit single precision FP) mega-function. I want to simulate the IP that I generated. I couldn't see any simulation file. Please, can you help me to generateSet up for LVDS SERDES IP for Cyclone 10 GX, need 96 TX with 16 CLKs.
