Most RecentIP licence for noncommercial project?Error 12006 when compiling clock bufferDoes a slow Avalon slave block the Lightweigh HPS-to-FPGA bridge?Can 2.5V Crystal oscillator be used for reference clk of DDR3L（1.35V）in C10GX？Why can PLL + LPDDR2 compile success in Quartus 17.1, but fail in 13.1?Embedded attributes inside AVSPI core fail during compile2Gb setting with PFLwhat is the option to initiate the DDR3L calibration? how long it will take to complete the calibration?do the LPM_SHIFTREG must be used in the spi serial receiving code when the clock fequency is too fast?XXX. Sof was downloaded to FPGA, Contains a 5G LDPC IP,i find the signal (sink_ready) always low,
