Most RecentIntel Customer Support - Case #: 04747478Sampling MAX 10 TSD using ADC Control Core running at 1 MspsCurrent demand of Max 10 JTAG pins.LVDS SERDES using external PLL from IOPLLwhy pcie_tx_st_ready keep low for almost 16384 pcie_clkMSIx Capability registers and TPH capability Registers.RGMII data not passed to AvalonSTAvalon-MM slave shows constant high reg_busy signal (TSE IP).Stratix 10 SX simulation fails with ERROR: iossm_bf_cpu_cpu_test_bench/i_read is 'x'LVDS Serdes multi channel bit order (Cyclone 10 GX)
