Most RecentHi, I am trying to read flash device ID from our Arria 10 SoC based board. (Flash device is EPCQL512). I have used Intel FPGA Serial Flash Controller 2 and clock used for IPcore is10 MHz.Issues using ST-Avalon on Stratix 10 MX development KitBFM MM-Master Help for custom IPMAX 10 EMIF DDR3 velocity transfer issueHDMI Output Settingsnot able to generate sdo for arria 10 soc for post-synthesis timing simulationYour IP for 5G LDPC decoder has nearly 800 bits data (384 for sink_data and 384 for sour_data and others). Is it possible for ASIC designing? Is it so that 800 I/O pins for ASIC?Difficulty with Simple Socket Server Design ExampleIs the end of life for Stratix III and Stratix IV really 2023?Student license for FFT IP Core
