Most Recentstatus info INTELPackagingMax V Stencil Design 64-Pin Plastic Enhanced Quad Flat (EQFP)Cyclone V LVDS "programmable differential voltage" and "Pre-Emphasis"F-Tile PMA Direct PHY - USB3 - Enable per PMA lanes TX and RX ready signal issueF-Tile PMA Direct PHY - USB3 - - RX Termination Control (connect/disconnect)FPGA load on cyclone V GSRDCyclone V SoC GSRD precompiled SD boot failureJAM to JBC converter1SG085HN3F43E3VG eval board and FBGA-1760 footprint
