Most RecentIs there an example design available for doing an RSU across a UART discrete (without the use of a Nios II)? My target is the MAX10 but that isn't as critical. I would prefer VHDL over Verilog, but I will take what I can get.Failure analysis request for Intel part for 5CSXFC6C6U23I7NAfter PreSICE calibration ATX PLL doesn't lockMAX10 weak pull-ups and leakage currentIntel MAX10 LVCMOS and LVTTL Drive strength limitationsPin placement errorArria 10 SoC EMIF Input clock jitter requirmentPLL frequency doubling but shouldn'tprogram own design into the cfi flash device on arria v gx starter kitepf10k100ARI240-3 Need MSL
