Most RecentS10 ddr4 controller Internal Error Sub-system: OCT Line 2587How to set up Cyclon 10gx transceiver 10g base SR （Short Range 850nm MMF）/LR(Long Range 1310nmSMF )/ER？Can't pack to I/O pinHello, I'm using a Max V cpld on quartus, I tested my code on quartus with modelsim, it's working...and now I'm working on dev kit Max V but I didn't have any result... my question is how i can put my test bench on dev kit ( cpld) thank youPlease help me with a RMA. CISCO require a Failure Analysis in order to find the root cause.Need to request an RMA for failure analysis for a CPLDCyclone V ConfigurationI am looking for a RoHS 3 (EU2015/863) CoC for P/N 5M80ZE64C5N. emails to [email protected] are bouncing. Thank you, Greg BuchananPotential issues in receiving LVDS protocol data from external module using HSMC ConnectorsIs there a standard way for an FPGA Qsys system (Nios II) to access HPS pins?
