Most RecentI designed an FSM, and it's going to states that it shouldn't be able to go to. Please help me understand what my Verilog code is doing.I have a supplier using the DK-DEV-5CSXC6N. Using the on-board USB-Blaster circuitry they can successfully run debug sessions on both the HPS and the FPGA. However when using an external USB-Blaster not so much.At boot time Cyclone V from nand, gpio HPS not controlledCan the CPLD EPM7128AELC84-10 be compiled for with Quartus Prime?Hi, I have a DE1-SOC board but can not find a good tutorial for it!! Can you please help me?After software update of the DE10-NANO-sd-card the HDMI-port seems to be damaged. Is that possible or there other options to reset that?How do I report an error in Intel's document 150-0321321-A1 "Cyclone 10 LP FPGA Evaluation Kit Board"?Does the logic inside flash memory devices require a power down after each WRITE operation?HPS_CLK1 of 10AS016 : this is connected to 38.5Mhz of crystal. This can source the FPGA clock also right?DDI Port mapping to FPGA Pins
