Most RecentHow to enable parallel on chip termination for a LVDS input on Arria 5 GX Devices?Stratix V GX 100G Dev Kit JTAG Not WorkingStratix 10 development board failed to load configurationHow to setup a chain Linux->UART->GPIO_0 on de10-nano?Arria 10 GX FPGA Development Kit - standalone clock configurarion.I have a Stratix 10 Development Kit. Which target device should I choose in Quartus?Does anyone have a VHDL code for SVPWM? If anyone has it, can you email to me? or you can post in the answer Thank you so muchHi, We are looking for a solution which can convert Dual 4 line MIPI DSI to V-By-One 4K 60fps or 120Fps to drive an LCD panel. Alternately HDMI2.0 to V-By-One 4K 60fps or 120fps also in consideration. Can you give a suggestion?Soldering ball open after reflow and the slice analysis shows the ball open inside, what 's the problem of the soldering ball that might be?Error (10822): HDL error at triangular_carrier.vhd(21): couldn't implement registers for assignments on this clock edge
