Most RecentHow to proceed to send to analysis 1 pc ALC3-1AB310260004_REP / 5SGXMA7N2F45I3N?Event 111581 / How to proceed to send to analysis 2pcs ALC3-1AB310260004_REP / 5SGXMA7N2F45I3NEvent 113344 - How to send to analysis 1pc ALC3-1AB310260004_REP / 5SGXMA7N2F45I3NArria 10 : HPS to FPGA Bridge EnableI require an Intel DSP board which support Intel MKL library and programming language is C or Python (Python is preferable). Additional requirement is 16 bit (12 bit will also be okay) ADC and DAC with sampling frequency in Mega sample.I'm using ModelSim - INTEL FPGA STARTER EDITION 10.6c to simulate a design with the onchipflash IP. But I get the error : # ** Error (suppressible): (vsim-19) Failed to access library 'fiftyfivenm_ver' at "fiftyfivenm_ver".Does the arrow in Figure 9 and in Figure 25 about the holdup relationship of Same-Edge Capture Center-Aligned Output contradict each other in AN433?Hi all I bought recently a Chinese development board for MaxII epm1270t144c5n (Mars-1270-Pro CoreBoard). There is on the board a crystal oscillator. I don't understand why output signal of oscillator is sent to a CPLD IO (IO 127) instead of GLCK input ?Error in Signal Tap Logic AnalyzerWill JTAG USB Byte Blaster II work with MAX10 at 3.0V VCCIO?
