Salma_M_Intel
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Re: Error programming Intel Stratix 10 MX FPGA Dev Kit (A PMBUS error has occurred during configuration)
Attached is the qsf. I am trying to use the PCIe EP edge connector and QSFP ports (QSFP ports are using a QSFP28 DD cable in loopback) Any help in what the problem could be would be much appreciated!2.8KViews0likes0CommentsError programming Intel Stratix 10 MX FPGA Dev Kit (A PMBUS error has occurred during configuration)
Here is the error. I will attach the qsf file subsequently. Info: Command: quartus_pgm -c 1 --mode=jtag top.cdf Info (213045): Using programming cable "Intel Stratix 10 MX FPGA Development Kit [1-12]" Error (18950): Device has stopped receiving configuration data Error (18948): Error message received from device: Detected hardware access error. There is a failure in accessing external hardware. (Subcode 0x0032, Info 0x00000000, Location 0x0000C400) Error (20072): A PMBUS error has occurred during configuration. Potential errors: Incorrect VID setting in Quartus Project. The target device fails to communicate to smart regulator or PMBUS Master on board. I am using Quartus 19.1 I am using Stratix 10 MX Dev Kit with Device: 1SM21BHU2F53E2VGS12.9KViews0likes4CommentsRe: Problem configuring PCIe Endpoint on Stratix10 MX Development Kit
I would appreciate a reference example that works using the Stratix MX using Avalon Memory Mapped (Avalon-MM) Intel Stratix 10 Hard IP+ for PCI Express”. The part number is 1SM21BHU2F53E2VGS1. I am using the SMX Kit listed on this page: https://www.intel.com/content/www/us/en/programmable/products/boards_and_kits/dev-kits/altera/kit-s10-mx.html1.6KViews0likes0CommentsProblem configuring PCIe Endpoint on Stratix10 MX Development Kit
I am using the Stratix 10 MX Development Kit. I am using an Example Design I generated in Quartus for “Avalon Memory Mapped (Avalon-MM) Intel Stratix 10 Hard IP+ for PCI Express”. I am using Quartus 19.4 I get this error on programming at about 80% done: Error: Device has stopped receiving configuration data Error message received from device : Device is in configuration state Operation failed Googling finds this workaround: https://www.intel.com/content/www/us/en/programmable/support/support-resources/knowledge-base/component/2019/error---device-has-stopped-receiving-configuration-data-error-me.html To avoid this error and to enable 3V IOs in a design targeting any variant of Intel Stratix 10 FPGAs, power up the VCCR_GXB and VCCH_GXB rails of the respective transceiver tile as per the Intel Stratix 10 Device Family Pin Connection Guidelines. How is this workaround implemented?Solved1.7KViews0likes5CommentsLTSSM in State 0xF, but BIOS does not POST
I have an Arria 10 SoC connected to a PC's PCIe Gen3x16 Slot. The connector is an FMC to PCIe x8 connector. I can see using Signal Tap that the FPGA's LTSSM in state 0xF. However BIOS does not POST. With the FPGA disconnected, the PC boots up just fine. Also if I replace the FPGA with another card, the PC boots up just fine. The exact same setup, same design, cables, has worked successfully on another motherboard. What should I be looking at next? Any ideas?1.4KViews0likes0Comments