Salma_M_Intel
New Contributor
New ContributorProblem configuring PCIe Endpoint on Stratix10 MX Development Kit
I am using the Stratix 10 MX Development Kit. I am using an Example Design I generated in Quartus for “Avalon Memory Mapped (Avalon-MM) Intel Stratix 10 Hard IP+ for PCI Express”. I am using Quartus ...
Hi,
This is to let you know that we tested 1SM21BHU2F53E1VG with the Avalon-MM design that generated from the PCIe GUI. It is working fine. The 1SM21BHU2F53E2VGS1 is the engineering sample device, and this board is currently not available for testing.
When you generate the example design from the PCIe IP AVMM GUI, did you select "Stratix 10 MX H-Tile ES1 FPGA Development Kit"?
Regards -SK
