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LZhao1
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After reconfiguration the phase of a PLL, The oscilloscope can't detect the change
Perform a dynamic reconfiguration to a PLL to change phase refer to AN661, we can see a correct function in both simulation and STP, but when output the clock to a FPGA pin, use a oscilloscope to monitor，cannot find any change on oscilloscope screen.Re: Why NCO IP outputs ZERO?
Hi, We found that in Quartus 19.2pro, some .hex files generated by NCO IP has a mismatch location where system needs, so we manually move those .hex files to correct location, then, NCO IP can function right. Maybe in Quartus 19.4pro can fix the problem, I have not verify yet.
