SparkyNZ
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Error (276003): Cannot convert all sets of registers into RAM megafunctions when creating nodes.
Error (276003): Cannot convert all sets of registers into RAM megafunctions when creating nodes. The resulting number of registers remaining in design exceeds the number of registers in the device or the number specified by the assignment max_number_of_registers_from_uninferred_rams. This can cause longer compilation time or result in insufficient memory to complete Analysis and Synthesis I started doing some overhaul on the logic in my project today and I got this error. I've made too many changes to incrementally back-step to see what caused this. How can I identify what the offending code, logic or register usage actually is? I can't see what my total register usage is yet. I'm using my trusty Cyclone IV EP4CE6 FPGA. I know I have been close to exhausting resources on this device for a while. I have the below array which has usually been a problem, but even when I reduce the size right down it isn't making any difference so it must be something else. bit[2:0] frameBuffer[49920]; I have been trying to work through resolving all of my truncation warnings etc today but still no joy. I did however see this in the log: Info (276014): Found 1 instances of uninferred RAM logic Info (276007): RAM logic "frameBuffer" is uninferred due to asynchronous read logic What does this mean? I am only reading frameBuffer in one place as far as I can tell: bit[16:0] frameBufferReadIndex; bit [3:0] frameBufferByte; bit vgaReading; assign frameBufferByte = vgaReading ? frameBuffer[ frameBufferReadIndex ] : 4'h0; Ignore the 'byte' reference - I have been making the 'byte' smaller and smaller since I began running out of resources.Re: Making Nodes visible to SignalTap
I tried (* preserve_for_debug *) in VgaDisplay.sv but that still won't show vic_screen_lines in STP. I tried "Design Filter (all names)" as well - it still doesn't appear when I click List. It is not listed in the 2 optimization result reports for removal, I can't find it in the compilation output, and I certainly can't see it in the RTL Viewer so it must have been removed somehow. BUT.. I have just this minute tried searching for *vic_screen_lines* - and it appears! So I will have to remind myself to always use the asterisks either side of the node. I feel so stupid now - thank you for joining on me on this journey. 🙂 Always surround with asterisks, Sparky! Always!Re: Making Nodes visible to SignalTap
The only reason I mentioned Notepad is that I find editing text faster than going into the Quartus UI screens. Just saying that if I can "decorate" registers/nodes withing the Verilog text, that's easier than fiddling with the Assignment Editor.. However.. I do seem to have hit the pin limit where I may need to do what you suggested anyway: What is my logic connected to? Well.. I had hardcoded a load of constants that need to become variable. Once I did that, the logic didn't seem to work the way I expected it to so I thought I would "promote" the nodes to outputs so I can see what values they are taking on in SignalTap.. Maybe I have far too many interdependencies here and perhaps I need to take a step back and simplify what I have. The last 5 signals I refer to in my VGAController module - it decides where to paint a border or a screen background.. as the old Commodore Vic 20 used to. I know what I am doing it bad because I am including so much arithmetic now. It wouldn't have mattered with the constants.. but pretty bad to implement that complicated mess in logic.
