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SparkyNZ's avatar
SparkyNZ
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1 year ago
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Error (276003): Cannot convert all sets of registers into RAM megafunctions when creating nodes.

Error (276003): Cannot convert all sets of registers into RAM megafunctions when creating nodes. The resulting number of registers remaining in design exceeds the number of registers in the device ...
Hdl
  • FvM's avatar
    FvM
    1 year ago

    Internal FPGA block RAM is synchronous, using a clock. If your code doesn't register at least frameBufferReadIndex, it can't infer RAM. Best to follow RAM code template in Quartus.

    For maximum memory size, you also need to look at RAM block organization. RAM capacity of EP4CE6 is 30k x 9bit, thus you can't implement more than 30k 4-bit array elements.

SparkyNZ's avatar
SparkyNZ
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1 year ago

Well.. I implemented my frameBuffer as a separate module as suggested here: https://www.intel.com/content/www/us/en/docs/programmable/683082/22-1/simple-dual-port-dual-clock-synchronous-ram.html

..and that is compiling and "working" once again. Now I have this warning, so I assume all is OK and back to normal?

Warning (276027): Inferred dual-clock RAM node "FrameBuffer:frameBuffer|ram_rtl_0" from synchronous design logic.  The read-during-write behavior of a dual-clock RAM is undefined and may not match the behavior of the original design.