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SparkyNZ's avatar
SparkyNZ
Icon for Contributor rankContributor
1 year ago
Solved

Making Nodes visible to SignalTap

When I want to view nodes in SignalTap, I sometimes have to comment out my nodes and put them into module outputs and then into top level outputs in order to see them. Isn't there an easier way of d...
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  • SparkyNZ's avatar
    SparkyNZ
    1 year ago

    I tried (* preserve_for_debug *) in VgaDisplay.sv but that still won't show vic_screen_lines in STP. I tried "Design Filter (all names)" as well - it still doesn't appear when I click List.

    It is not listed in the 2 optimization result reports for removal, I can't find it in the compilation output, and I certainly can't see it in the RTL Viewer so it must have been removed somehow.

    BUT.. I have just this minute tried searching for *vic_screen_lines* - and it appears! So I will have to remind myself to always use the asterisks either side of the node. I feel so stupid now - thank you for joining on me on this journey.

    Always surround with asterisks, Sparky! Always!

sstrell's avatar
sstrell
Icon for Super Contributor rankSuper Contributor
1 year ago
I mean supply a clock and create registers to store the values. Basic RTL design practice.
SparkyNZ's avatar
SparkyNZ
Icon for Contributor rankContributor
1 year ago

Oh, so if the registers aren't modified on a clock cycle (ie. within an always block or state machine), then maybe registers are not inferred? Is it possibly because I have "continuous" logic here rather than clocked (flip-flop) logic?

Please excuse my limited experience - I'm still a beginner/dabbler. Maybe it would be good for me to scale down a smaller project and see what is actually produced in the RTL Viewer.