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cosx

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Re: STA failed during rapid recompilation
Hi Nurina, Sorry for the late reply as I just graduated from university and was having a trip. Thank you very much for your and since the problem is not supported, I would probably change to a modern version of compiler. Best Wishes, Mingqiang
4 years ago Place Quartus® Prime
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Re: STA failed during rapid recompilation
Sure! In order to reproduce the errors, all error files need to be restored to the original project. Here is the step: 1, Cut all files in the error_file6 into the db folder in the error_file2. 2, Cut all non-folder files in the error_file8 into the incremental_db folder in the error_file4. 3, cut all folder from the error_file2 to error_file8 into the float_add_mult folder in the error_file1. 4, the error_file1 is now the original project. After doing these, open the float_add_mult project top.qdf files. Then use Quartus 15.1 standard edition to perform full compilation. (Or use command "quartus_sh --flow compile top -c top" from linux terminal.) You will reproduce the error. Thank you! Mingqiang
4 years ago Place Quartus® Prime
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Re: STA failed during rapid recompilation
Hi Nurina, Thank you very much for your reply! I firstly correct myself that at the full compilation stage this error occurs, not just at rapid recompilation. The original file is too big to contain even after compression and so I attach a similar project without compilation. This project is based on Quartus 15.1 standard edition installed on Linux. If you compile this project directly using the command below, you are likely to find the error attached above. aoc -v .aoco (project directory) --board c5soc I personally also has some finding of the errors and would like to share them here. The text file that records the whole compilation flow of the project is attached as error_file.txt. The errors are at line 8008 and 8009. There are some lines just before the error (line 8005-8007): Info: kernel clk has period: 404.996 Info: kernel clk has multby: 1 and divby: 454 Info: Using adjusted multby: 404996 and divby: 510112584 Multiplying and dividing numbers in these lines give rise to the overflow and probably this is the reason for the error. Look at these numbers at the stage just after adjust_plls.tcl being called (Line 7417-7424): Info: Solved VCO for C 454: 404.059997201 8 1 1362309 4000 20 2 (vco m n k r cp div) Info: Computed PLL settings: fmax m n k c0 c1 r cp div Info: Computed PLL values: 0.889999993835 8 1 1362309 454 227 4000 20 2 Info: finfpd 50.0 Info: post-div fvco 404.059997201 Info: true fvco 808.119994402 Info: kernel_fmax 0.889999993835 Info: kernel2x_fmax 1.77999998767 One can see that after pll adjustment, the clock speed is determined to be maximum of 0.89MHz (0.8899999) which is nonsense. Then look at the VCO period 404.059997201, and the multiplier (n=1) the divider (c0=454), they all occur in the lines before the error. In order to compensate this 404.996 MHz to be 0.89MHz, the system makes decision: *404996 /510112584. Since the smallest frequency the PLL can achieve is not even 0.89MHz, these numbers do not make sense at all and thus cause errors in the STA. Above are my analysis and further investigation fount that the slack at line 7341 compensates the clock frequnecy is -1103.311!! This is a huge number and that is why the clock frequency is so low!! However, I am not sure whether my analysis is absolutely correct and also I am not sure why Quartus gives such large slack. Therefore, I would still kindly ask help if you can help me solve this problem. Thank you again! Mingqiang
4 years ago Place Quartus® Prime
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STA failed during rapid recompilation
Hi everyone, I came across a strange problem in Quartus 15.1 standard edition. The error is at rapid recompilation step whenever I add instrument circuits in the old design. This error is shown below: Internal Error: Sub-system: STA, File: /quartus/tsm/sta/sta_clock_mgr.cpp, Line: 2363 Integer overflow occured when trying to find the "multiply_by" or "divide_by" parameter of the generated clock the_system|acl_iface|acl_kernel_clk|kernel_pll|altera_pll_i|cyclonev_pll|counter[0].output_counter|divclk Stack Trace: 0x3034eb: STA_CLOCK_MGR_IMPL::initialize_derived_clock(STA_CLOCK*) + 0xdab (tsm_sta) 0x305eb1: STA_CLOCK_MGR_IMPL::identify_ignored_clocks_recurse(STA_CLOCK*) + 0x51 (tsm_sta) 0x30620f: STA_CLOCK_MGR_IMPL::initialize_derived_clocks() + 0x7f (tsm_sta) In Quartus 19.1, this error was solved by adding set_global_assignment -name DISABLE_LEGACY_TIMING_ANALYZER ON However, this solution did not work for Quartus 15.1 because this command would cause errors. May I ask if anyone has come across this situation before? Thank you in advance! Mingqiang
Solved
4 years ago Place Quartus® Prime
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Re: HLS compiled qsys modification and regeneration problem
Hi everyone, A new update here: when I use aoc -v to compile the project, some strange messages occur: com.altera.hdlwriter.EntityWritingException: Connection is not connected float_add:avm_local_bb1_ld__inst0 -> ? at com.altera.hdlwriter.internal.OldEntityWriterInternal.addConnection(OldEntityWriterInternal.java:431) at com.altera.hdlwriter.internal.OldEntityWriterInternal.writeHDLInternal(OldEntityWriterInternal.java:122) at com.altera.hdlwriter.internal.EntityWriter.writeHDL(EntityWriter.java:40) at com.altera.sopc.generator.EnsembleGenerationFileSet2.generate(EnsembleGenerationFileSet2.java:61) at com.altera.sopc.generator.FileSet2.generate(FileSet2.java:150) at com.altera.sopc.generator.Sellafield.generate(Sellafield.java:366) at com.altera.sopcmodel.sbtools.sbgenerate.SbGenerate.performGeneration(SbGenerate.java:518) at com.altera.sopcmodel.sbtools.sbgenerate.SbGenerate.act(SbGenerate.java:464) at com.altera.utilities.AltCmdLineToolBase.runTheTool(AltCmdLineToolBase.java:718) at com.altera.sopcmodel.sbtools.sbgenerate.SbGenerate.main(SbGenerate.java:965) May I ask has anyone come across this before? It seems that my defined IP has problems, but don't know why it has problems.. Thank you again! Mingqiang
4 years ago Place FPGA Device
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Re: Fractional PLL fitting Problem Error 11239
Hi Mr. BB, Thank you so much for your reply! The BSP I used was the acl_kernel_clk, acl_kernel_iface from the opencl platform. I modified the acl_kernel_clk and add extra PLL modules for multi-clock applications. The board I used was cyclone V "c5soc". I have also attached the modified acl_kernel_iface and kernel_clk for your references. (The Quartus version used to compile this system was 15.1.) Thank you for your help! Mingqiang
4 years ago Place FPGA Device
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HLS compiled qsys modification and regeneration problem
Hi everone, I came across a question about modifying HLS generated qsys and regeneration of the modified system. My quartus SDK compiler is 15.1. I compiled a .cl file using command "aoc -s -v ().cl --board (board_name)". A qsys named system.qsys had been generated. Next I modified this system by adding some customised components. After saving ths system, I regenerated this system.qsys into .v file. The command I used for regenerate was 'qsys-generate system.qsys --synthesis=VERILOG --family="CYCLONE V" --simulation=VERILOG'. After doing this, however, the system.v was not shown in the synthesis folder. Nor was it shown in simulation folder. Before regeneration, I had already removed all HLS generated system folder and "system.tcl" file. However, the system.v was still not there. May I ask if the .v file has been hidden or something else happened? I have also attached the whole project for your references. Thank you very much! Mingqiang
4 years ago Place FPGA Device
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Re: Custom IP Composed Component generation using _hw.tcl
Thank you so much for your reply! My second point is more about composed IP generation. Currently the document did not give any example code of the whole generation. For instance, if I have a composed IP that contains 3 sub customised IPs, how can I generate this composed IP? Do I just need to add synthesized fileset of all files and then the composed IP .v is generated, or need extra commands? Could you please give me a bit more details of this if possible? Thank you again! Mingqiang
4 years ago Place IP & Transceiver
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Custom IP Composed Component generation using _hw.tcl
Hi everyone, I came across two problems when reading IP generation part of "Intel® Quartus® Prime Pro Edition User Guide Platform Designer 20.1 version" and I would like to kindly ask for assisstance. Question one is at page 134, the example of generating the component using script "generate_my_custom_hdl $... .().sv". May I ask what is "generate_my_custom_hdl"? Without this, are there other commands in the generate_callback proc to generate the .sv IP? Question 2 is at page 136, example of designing composed components. From this example, I am not sure what file_set_file I need to add if I want to generate this IP. This IP have 4 instances, with two of them being customized one. Sometimes a customised IP may have multiple synthesis file in their QUARTUS_SYNTH file sets. Do I only need to add the custom IP file or the whole file sets behind them? For instance, if "my_regs_microcore_hw.tcl" has my_regs_microcore.v, verilog1.v, verilog2.v...verilogn.v; do I need to only add the my_regs_microcore.v for composed component or all these files? Thank you in advance! Mingqiang
Solved
4 years ago Place IP & Transceiver
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Re: Customised IP parameter Problem
Thank you so much for your help! I also found the problem myself. Indeed the _hw.tcl does not allow get_parameter_value command. I actually redesign a top level module that contains lsu_ic_top.v and assign the parameter values from qsys level. Thank you for your help still! Best wishes, Mingqiang
4 years ago Place IP & Transceiver
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