XG_Kang
New ContributorUser Profile
New Contributor
User Widgets
Contributions
Errors in Arria 10 device
I have a design using 10AX057N4，and about 70% ALMs are used. In a low-level module in the design , I define one single-bit input port to constant "1", below module is for example not the real design: module_aaa inst0 ( .a (a), //input port a .b (1'b1), //input port b, reference to constant 1 .c (c) //output c ); and for a very low probability , I can find that port b will physically be constant '0' . Why? what cause this error?1.1KViews0likes2CommentsDoes repeater/retimer be need when Arria10 GX FPGA used in backplane application?
two boards are assembled on a backplane with a distance about 50cm. Two Arria10 GX FPGAs are located on these two boards seperately, connecting to each other with Arrria 10 GX transceiver。Does repeater or retimer be need in this application? The data rate is about 6~8Gbps。400Views0likes0CommentsDoes repeater/retimer be need when Arria10 GX FPGA used in backplane application?
two boards are assembled on a backplane with a distance about 30cm. Two Arria10 GX FPGA are located on these two board seperately, connecting to each other with Arrria 10 GX transceiver。Does repeater or retimer be need in this application? the data rate is about 8Gbps。Solved740Views0likes1CommentRe: how do data in rpd file map into configuration flash with arria10
Thanks for your reply. Are there any document or application note descripting the mapping between rpd file and its corresponding jic file? It is very curious that I send rpd data to flash started from address 0x0000_0000 ，FPGA Configuration works correctly。According to Map file, rpd data should send to flash started from address 0x0000_0020。Could Intel give definite discription?1.6KViews0likes0Commentshow do data in rpd file map into configuration flash with arria10
RPD file usually is used to update configuration flash。when using Arria 10 device，full compiling will generate a map file, this map file give the information that configuration data starts at 0x0000_0020 for Arria10 device。My question is : should the first byte in RPD file send to address 0x0000_0020 at flash ,or, should the first byte in RPD file send to address 0x0000_0000 at flash? Where I can find detailed descriptions? Thanks.Solved1.6KViews0likes4Commentswhy pcie_tx_st_ready keep low for almost 16384 pcie_clk
My FPGA design sends continueous MWr TLP packets to CPU module on pcie gen2x4 link。The fpga design use Intel's Arria10 PCIE HIP 。When sending contineous MWr TLP packets，the tx_st_ready signal of the PCIE HIP will be pulled down for almost 16384 pcie_coreclk cycles sometimes, and will be return to high for ready receiving TLP。Why the tx_st_ready signal be pulled down for so long cycles?how to shorten these low cycles?Solved774Views0likes2Comments- 1.2KViews0likes1Comment