AleCampla
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Re: Developer Zone Premier but OneAPI FPGA add-on can't be download
Dear @Josh_Intel , thanks for your reply. Yes, Linux. I tried the online download via wget https://registrationcenter-download.intel.com/akdlm/irc_nas/18487/l_BaseKit_p_2022.1.2.146.sh sudo sh ./l_BaseKit_p_2022.1.2.146.sh where the FPGA addon is available (but not the 21.3, only previous version). And that was in general not problematic. (While the docker installation does not contain it.) Which other mechanisms are you referring to for FPGA addon download? I am not sure I am aware of them. Best regards Alessandra2.8KViews0likes0CommentsRe: Developer Zone Premier but OneAPI FPGA add-on can't be download
Dear @Rahila_T_Intel can this be solved soon? It's already a month that I am going back and forth between different supports (chats, emails, forum) without any real help. This is quite puzzling. I am considering to abandon OneAPI, and discourage my colleagues at CERN to use it. Best regards Alessandra2.8KViews0likes0CommentsRe: Developer Zone Premier but OneAPI FPGA add-on can't be download
Hi ! Thanks for your reply 🙂 The page you posted is exactly the link where I am facing this account issue. E.g, when I click on the "FPGA add-on for custom platforms using Intel Quartus software 21.3 for Linux" at this link here, I get redirected to this other link. And then I enter the unpleasant "loop" mentioned above. This happens for all the different quartus versions add-on. Best regards, Alessandra2.9KViews0likes0CommentsDeveloper Zone Premier but OneAPI FPGA add-on can't be download
Hi, my account seems to be already setup for being on the Developer Zone Premier. But when i try to download the FPGA add-on for custom platforms I am anyway redirected to the "Request access" page. And when I click it, I get the message "You are already registered for Developer Zone Premier". So even if I am logged in, there is no chance to download the tool. I have been already exchanging some messages with the Developer Zone Support that said they can't help on this matter, and to write in the forum. I sincerly hope this can be solved soon. Best regards, Alessandra3KViews0likes14CommentsS10 MX PHY: signal rx_is_lockedtodata unstable during hardware test
Hi, I am trying to establish 1G communication between my laptop and a dev kit with s10 MX. My designed is based on the 1G/2.5G linked here. As the devkit does not have an RJ45 connector (and as i need only one transceiver line) I am using : 1) https://www.fs.com/de-en/products/72588.html 2) https://www.fs.com/de-en/es/products/66616.html?currency=EUR&paid=google_shopping&gclid=CjwKCAiAp5ny... But rx_is_lockedtodata signal is not stable, it continuously flickers, causing the rx_digitalreset from the reset controller to flicker as well (picture from signaltap attached). I thought it might be due to a failure in the auto-negotiation. I checked the PHY registers with the system console, and that's what I get: % CHKPHY_STATUS PHY Control = 0x140 PHY Status = 0x9 PHY ID 0 = 0xC01A PHY ID 1 = 0xC0CA Dev Ability = 0x1A0 Partner Ability = 0x0 AN Expansion = 0x0 IF mode = 0x0 According to the PHY documentation (Table 15) the Bit[3] of the status register set to 1 means that there is auto-negotiation capability. Bit [12] of the control register corresponds to AUTO_NEGOTIATION_ENABLE and for me it is currently at 0, but I imagine I need to switch to 1. But when I try to use the command "SETPHY_CL_37_AN" that would send "reg_write 0x00018000 0x00 0x1140" (commands taken again from the example designs here), the PHY control register remains at 0x140. I checked addresses and bits. And their are actually correct. Question one: is actually auto-negotiation the problem? Question two: why I am not capable of writing that specific register? (I can switch between 1G/2.5G config without problems). It's worth to mention that in simulation the rx_is_lockedtodata gets locked. In that case I inject (random) data into the gmii side of the PHY and loopback tx and rx. Thanks in advance for the help. Alessandra939Views0likes2CommentsRe: Stratix 10 1G/2.5G Ethernet reconfiguration not working in hardware
Hi dlim, I finally managed to communicate with the PHY. One problem was that some of the switches were not in the right position, so the pointer in the scripts was not pointing to the S10 FPGA. Also a reset_n on the fw side was not negated (and so it was always in resetting all the time). This is then solved. A part for one register (for auto negotiation enabling) that I can't write. But I would open a new ticket for that. Thanks for your support. Alessandra1.9KViews0likes0CommentsRe: Stratix 10 1G/2.5G Ethernet reconfiguration not working in hardware
Some more information: Trought the get_service_paths master I discovered that the script was pointing to the wrong object on the jtag chain. It was set to 0, but now it's set to 1 (the stratix 10 MX on the devkit) % get_service_paths master {/devices/10M16S(A|C)@2#USB-1#Intel Stratix 10 MX FPGA Development Kit/(link)/JTAG/(110:132 v1 #0)/phy_0/master} {/devices/1SM21BHN(1|2|3)|1SM21BHU1|..@1#USB-1#Intel Stratix 10 MX FPGA Development Kit/(link)/JTAG/(110:132 v1 #0)/phy_0/master} {/devices/VTAP10@3#USB-1#Intel Stratix 10 MX FPGA Development Kit/(link)/JTAG/(110:132 v1 #0)/phy_0/master} Still, I have no success as the requests timeout. % set port_id [lindex [get_service_paths master] 1] /devices/1SM21BHN(1|2|3)|1SM21BHU1|..@1#USB-1#Intel Stratix 10 MX FPGA Development Kit/(link)/JTAG/(110:132 v1 #0)/phy_0/master % open_service master $port_id % master_read_32 $port_id 0x50000000 1 error: master_read_32: This transaction did not complete in 60 seconds. System Console is giving up. while executing "master_read_32 $port_id 0x50000000 1" And no signals are propagated after the JTAG bridge.. could it be that the development kit of the S10 MX needs to be setup somehow?2KViews0likes0CommentsRe: Stratix 10 1G/2.5G Ethernet reconfiguration not working in hardware
Hi, I have been testing a bit more. In simulation, injecting the avalon MM commands directly after the JTAG bridge to e.g. change the configuration of the PHY works well. So it's not a problem of the address mapping block. To make sure that the read/write commands are actually propagated in hw, I added some counters on the read/write signal (simulation is ok). BUT when I move to hardware and I launch the commands from the console, nothing is exiting the JTAG bridge. No counter is increasing, they all stay at zero. It looks like, either the scripts or the Bridge is having an issue. I am no sure on how to proceed with the debug. Let me know if you have suggestions. Best regards, Alessandra Ps. more info on how I am using the console. (i) Opening Quartus, (ii) uploading the firmware, (iii) opening the debug console. I cd to the folder were the scripts are and after sourcing the main.tcl I am writing: reg_write 0x000000 0x0 0 reg_write 0x000000 0x4 [expr ((1 << 16) | (0 << 0))] that are the very same commands written in the rcfg/mge_rcfg_inc.tcl file (always from the example project) simply with the numbers explicitly written. (My MGE reconfig module has base address 0x00000000, like in the example project.) And these correspond as well to the avalon mm commands that in simulation work.2KViews0likes1Comment