itchalfon
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Script or Tool in Quartus 18.1 to Extract RTL File List for Xcelium
Hi, Hello, I am working with Quartus Prime Standard 18.1 and need to generate a file (rtl_files.f) containing all VHDL and Verilog source files used in my Quartus project. This file will be used as an RTL file list for Xcelium's xrun simulator. Currently, I can extract file lists manually from the .qsf file, which contains set_global_assignment -name VHDL_FILE and set_global_assignment -name VERILOG_FILE entries. However, the .qsf also includes .qip (Quartus IP) files, which do not directly list the underlying Verilog/VHDL files used by the IP cores. I need a way to extract not only the files listed directly in the .qsf but also the actual RTL files referenced inside each .qip file so that rtl_files.f includes all necessary sources for Xcelium xrun. Could you provide guidance on: Any built-in Quartus commands, scripts, or tools that can generate a complete RTL file list (including files inside .qip)? Alternative ways to achieve this efficiently within Quartus 18.1? I would appreciate any official documentation or recommended methods to automate this process. Thank you for your support! Best regards, Itshak ChalfonRe: Programming failing in DE10-Nano board (And in my board as well)
Hi Fakhrul, I have tried all of the above suggestions, but it still doesn’t work. I am unable to program the flash. I also tried configuring the FPGA as the only device in the JTAG chain, but that didn’t work either. Thanks, ItshakRe: Programming failing in DE10-Nano board (And in my board as well)
Hi, It seems that the flash device actually on board is EMCS64. (However, on the DE10nano design scheme, they put S25FL128.) After updating the flash device, The following messages were: (See snapshot above as well) Info (209060): Started Programmer operation at Tue Dec 31 09:44:49 2024 Info (209016): Configuring device index 2 Info (209017): Device 2 contains JTAG ID code 0x02D020DD Error (209040): Can't access JTAG chain Error (209014): CONF_DONE pin failed to go high in device 2. Make sure all communication cables are securely connected, select a different device, check the power on the target system, or make sure all nCE pins are connected to GND. The Intel FPGA Knowledge Database contains many articles with specific details on how to resolve this error. Visit the Knowledge Database at https://www.altera.com/support/support-resources/knowledge-base/search.html and search for this specific error message number. Error (209012): Operation failed Info (209061): Ended Programmer operation at Tue Dec 31 09:44:59 2024
