HBhat2
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Re: Arria 10 FPGA Unpowered State
Hi Amin, "The Arria® 10 device dedicated transceiver pins are not subject to the same hot-socketing limitations of the general purpose I/O pins. It is OK to drive the dedicated transceiver pins during power-up and power-down sequencing of Arria 10 devices." Above statement is confusing with "Fully configure the transceiver block before driving or having any activity on the Intel Cyclone 10 GX and Intel Arria 10 device transceiver pins." This statement is in the below link. "1.3.2. Transceiver Pin Guidance for Unpowered FPGA " page 14 https://www.intel.com/content/dam/www/programmable/us/en/pdfs/literature/an/an692.pdf Is it possible to correlate above statement with statement in an692? With Regards, HPBRe: GPIO state of ARRIA 10 FPGA during Power up & during configuration
Hi, Thank you for the response. 1) Before and during configuration, all user I/O pins are tristated. 2) Stratix® series, Arria® series, and Cyclone® series have weak pull-up resistors on the I/O pins which are on, before and during configuration I just confused with these 2 points. Point 1) says IO pins are tristated. & point 2 says IOs have weak pull-ups. My confusion is if weak pull up is connected to IOs before & during configuration, what is the meaning of tristated (point 1)? Whether this means that the internal IO buffers of FPGA is not connected to the pins (tristated) but FPGA IO pins are pulled up with resistors so that when we physically measure the voltage before or during configuration, we can get VCCIO voltage level? With regards, HPBGPIO state of ARRIA 10 FPGA during Power up & during configuration
Hi, I want to know whether the GPIOs in the arria 10 GPIO bank remain in High impedance/Tri-state during power up sequencing. Where I can get the information regarding this. Which document clear mentions this point. I gone through Arria 10 handbook & pin connection guidelines. Nowhere the IO state of Arria 10 FPGA during power up is mentioned. Please provide the appropriate reference to know what will be the state of IOs during FPGA power up (& during configuration). With regards, HPBS-10 Transceiver IO Terminations
Hi, I am using stratix 10 SoC dev kit with Transceivers with 10Gbps speed. There, I want to use External termination for the transceiver receiver pins. As per the L tile user guide, we can set r_unused option in the native PHY.[Table 23. RX Analog PMA Settings Options] I checked setting the same in Native PHY, the error message is listed saying that r_unused as invalid. What is the procedure to set external termination for receiver pins? Also, I checked with "set_instance_assignment " commands & seeing no impact on these commands. set_instance_assignment -name HSSI_PARAMETER "pma_rx_buf_term_sel= r_unused" -to AH45 set_instance_assignment -name HSSI_PARAMETER pma_rx_buf_term_sel= r_unused -to AL43 With Regards, HPBRe: Stratix 10 Native PHY PMA register details for reverse serial loopback
Hi dlim, I am aware of reverse serial loopback not supported in GXT speed (More than 17Gbps). What I mentioned previously is the transceiver channel whichever I am using is GXT capable (In L-tile all channels can not support upto 26Gbps). But, the channels are configured @10.3125Gbps rate. With Regards, HPBStratix 10 Native PHY PMA register details for reverse serial loopback
Hi, Board: Stratix 10 SoC Kit- L-tile. I am accessing PMA registers to configure the transceiver pairs (GXT) in reverse serial loopback mode. As per the transceiver user guide: {0x11D[0], 0x132[5:4], 0x137[7], 0x144[1], 0x142[4]} : 6'b000000 - Disable reverse serial loopback 6'b100101 - Enable pre-CDR reverse serial loopback 6'b001010 - Enable post-CDR reverse serial loopback I have written the RTL to update this read modified write logic as well. Also, I have carried out one testing. Here, I have configured the required transceiver pairs to Reverse serial loopback mode using "Transceiver Toolkit" Then, I simply read the registers using Av-MM ports of Transceivers. I am observing the values different from the one which is mentioned in the userguide. I am observing {0x11D[0], 0x132[5:4], 0x137[7], 0x144[1], 0x142[4]} = 6'b000110 instead of the values mentioned in the user guide. So, Please clarify which is the correct configuration data to configure transceivers in reverse serial loopback mode (both pre-CDR & Post CDR) With Regards, HPB
