SEbbert
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Video Frame Synchronization to External Signal
Hi together, I am working with the Intel Video and Image Processing Suite on an Arria 10 FPGA. Our pipeline works so far but we have one use case which I can't seem to find an appropriate solution for. We have 4 separate video pipelines all build like this: Clocked Video Input II -> Clipper II -> Frame Buffer II -> Mixer II -> Clocked Video Output II Now we need to synchronize the output of all 4 pipelines to a single external signal. This is typically a square wave signal with the rising edge indicating the start of a frame. I am wondering if there is a way to instantly drop a frame and restart a new one on the rising edge of the external signal. Is it somehow possible with the Frame Buffer II IP core? Is there a way to implement the synchronization with built-in functionality of other cores from the Video and Image Processing IP Suite? In the documentation I couldn't find anything that seems to match this use case. Thanks in advance for your help.1.2KViews0likes2CommentsRe: Bug in quartus_pgm command line tool
Hi BB, unfortunately I can't share the qsys design or quartus project because it is part of a project at my workplace. I tried using the --read param and it shows the exact same behavior. When the filename is shorter than 16 characters it fails with "Error (18927): No CSR found at address 0x4E000000". I also built a minimal design only containing a Nios II, On-Chip Memory, JTAG UART, JTAG to Avalon Master Bridge, Avalon-MM Clock Crossing Bridge and the Serial Flash Controller Intel FPGA IP. With this design I can't reproduce the error when using the "quartus_pgm --nios2" command to write to or read from the EPCQ. Do you have an idea what could cause an error like this with the filenames? Best Regards2.6KViews0likes0CommentsBug in quartus_pgm command line tool
Hi, i have been using the quartus_pgm command line utility with the "--nios2" option lately to write a few bytes to the EPCQ of my Cyclone V GT Development Kit. I noticed that there is a bug related to the length of the flash filename being used. When I type quartus_pgm --nios2 --epcq --base=0x4c000000 --csr=0x4e000000 --instance=0 fix1.srec I get the following error message: Info: Command: quartus_pgm --nios2 --epcq --base=0x4c000000 --csr=0x4e000000 --instance=0 fix1.srec Info (18932): Using cable "USB-BlasterII [1-8]", device 1, instance 0x00 Info (18932): Resetting and pausing target processor: Info (18932): OK Error (18927): No CSR found at address 0x4E000000 Info (18932): Leaving target processor paused When I use the same file but rename it to a filename with 16 or more characters the exact same command works flawlessly. It also works when I start the command from a parent directory and give "<path to file>/fix1.srec" as parameter (as long as it has 16 or more characters in total) I attached the srecord file i was using as .txt file because .srec is not a supported format for attachments. Edit: Quartus Version 18.1.0 Build 625 09/12/2018 SJ Standard Edition2.6KViews0likes3CommentsRe: Design security key programming gone wrong!
Hi John, thanks for the quick reply. Yes, the FPGA runs unencrypted bitstreams. It just doesn't run with encrypted bitstreams that match the programmed non-volatile design security key. My issue step by step: - The Cyclone V GT DevKit is setup to use the Active Serial configuration scheme, booting from the EPCQ256 device -> MAX V is programmed with the correct .pof file and MSEL dipswitches are set accordingly. - I program a non-volatile design security with an EthernetBlaster II using the same .ekp file as always. - I program a .jic file to the EPCQ256 that was encrypted with the key used in the ekp file. - The FPGA does not configure successfully and the Load-LED is flickering - The FPGA configures successfully if I program an unencrypted .jic file to the EPCQ256 Is there really no way at all to find out what key was actually programmed? Maybe I can return the Board to you for finding out the actual key and compare it to the one in the ekp file? Best regards1.8KViews0likes0CommentsDesign security key programming gone wrong!
Hi everybody, we are working with the Cyclone V GT Development Kit and use the Intel Design Security Features of the Cyclone V Device Family. Recently we had some strange problems occur during programming the non-volatile key to some of our boards/devices. We use a EthernetBlaster II for programming and use a chain description file to make sure we always program the same key. I programmed the non-volatile key to a few development boards and for two of them it seems that somehow the key was corrupted during programming. These two boards won't work with our standard encrypted configuration files, only with unencrypted ones. First I thought that programming the non-volatile key was just unsuccesful and tried to do it again. The Quartus Programmer states, that a non-volatile key has already been programmed to the device. From the fact that the devices in question only work with unencrypted configurations and still have a non-volatile key set, i deduce that the key was corrupted during programming. What can i do? How could this happen? Best regards Sebastian1.8KViews0likes3CommentsEPCQ bootloader corrupted after powercycle
Hi guys, this is my setup: Cyclone V GT Development Kit (set to support active serial configuration) Nios II/f @ 125 MHz Reset vector memory: Serial Flash Controller (EPCQ) Reset vector offset: 0x01A0 0000 Reset vector: 0x4DA0 0000 Exception vector: ddr3 ram Serial Flash Controller Intel FPGA IP @ 25 MHz connected to Nios via Avalon-MM Clock Crossing Bridge Avalon-MM address mem: 0x4C00 0000 Avalon-MM address csr: 0x4E00 0000 DDR3 HMC as program/data memory Nios executes code from here after bootloader finished copying from epcq PIO for "Alive"-LED For setting this up I followed the instructions in the Embedded Design Handbook (section 5.2.3.4). I also convert the elf into a hex file with embedded boot_loader_cfi.srec and put the sof and hex file together in a jic with the convert programming files dialog. After flashing the jic to the EPCQ everything works fine. Now it sometimes happens, that the Nios won't boot after a power cycle -> LED doesn't start blinking. The FPGA configuration works fine -> CONF_DONE LED turns on. I can also still start the software from the Nios II SBT for Eclipse. In Debug mode I looked at the EPCQ memory with the memory monitor and compared the contents at the CPUs reset address (0x4DA0 0000) to the contents of the boot_loader_cfi.srec. In every case I could observe, the data of the bootloader was corrupted (a few bits were different from the original srec data but not always the same bits). I also could fix the boot problem by overwriting just the boot loader in the epcq with the quartus_pgm --nios2 command and the boot_loader_cfi.srec adjusted to the addresses for my specific setup. In my software I don't access the Serial Flash Controller at all. It is just there for booting. I also tried to use a hardware breakpoint while debugging my software to break execution on a write access to the memory address range of the bootloader... no write access detected so far. I couldn't reproduce the behavior while debugging the application, yet. What could possibly cause the epcq contents to get corrupted? How could I further debug this issue? Let me know if I forgot some information to understand this issue. Thanks in advance Sebastian1.1KViews0likes1Comment