JFrye2
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AXI-4 Memory Map to AXI4-Stream (or Avalon Stream) IP
Hello, I would like an IP that I can program a start address from an SoC's CPU address space and a length, and the IP will read the memory via AXI-4 and generate AXI4-Stream data transactions as it is allowed by downstream tready. Xilinx has an AXI-DMA IP for this. What is Intel's solution? I have not been able to identify a canned solution on this platform with this capability.2KViews0likes1CommentRe: Make script doesn't generate Preloader image for DE0-Nano board
You should abandon the idea of a separate preloader. It is now built into u-boot. You clone the altera-opensource/u-boot repo and point u-boot to the hardware-software handoff files and it will generate the preloader. The file you will be looking for after building u-boot is u-boot-with-spl.sfp. I am convinced there are bugs in their u-boot, but you should still be able to get the chip set up to run Linux. I suggest you take the time to read https://github.com/u-boot/u-boot/blob/master/doc/README.socfpga because it should clarify a lot of your confusion; it helped me a lot. I think you will want to use the socfpga_cyclone5_defconfig when building u-boot (that was the one I got to work; when I tried to use the one for my board, the DE1-SoC I got no console output which is kind of buggy). Clone the repo, point it to the Quartus project, configure it for socfpga_cyclone5_defconfig, and build. Put u-boot-with-spl.sfp on the A2 partition and you should be golden.1.8KViews0likes0CommentsRe: CycloneV U-Boot FPGA Load Fails: Code -6
@AhmedH_Intel , sorry for the delayed response. This is a custom design. I tried putting my question out on the u-boot mailing list and they redirected me back here since Intel maintains https://github.com/altera-opensource/u-boot-socfpga I am targetting DE1-SoC with the u-boot software from the repo above. I tried socfpga_cyclone5_defconfig and that led to the programming error. I also tried socfpga_de1_soc_defconfig and I didnt even get console messages when I booted when I used that configuration. I can send you a zip of the hardware design if needed. Thanks.3.4KViews0likes0CommentsCycloneV U-Boot FPGA Load Fails: Code -6
Hello, I am trying to program the FPGA of my CycloneV from U-Boot. It appears to be failing and I am not sure why. The exact u-boot commands are echo --- Programming FPGA --- echo -----Loading image------ # load rbf from FAT partition into memory fatload mmc 0:1 ${fpgadata} socfpga.rbf; # program FPGA echo -----Print filesize----- printenv filesize; echo -----Program FPGA------- fpga load 0 ${fpgadata} ${filesize}; # enable HPS-to-FPGA, FPGA-to-HPS, LWHPS-to-FPGA bridges echo -----Enabling IFs-------- bridge enable; What I am seeing during boot is the following Hit any key to stop autoboot: 0 449 bytes read in 3 ms (145.5 KiB/s) ## Executing script at 02000000 --- Programming FPGA --- -----Loading image------ 7007204 bytes read in 366 ms (18.3 MiB/s) -----Print filesize----- filesize=6aebe4 -----Program FPGA------- Command 'load' failed: Error -6 -----Enabling IFs-------- switch to partitions #0, OK mmc0 is current device What does the error code -6 mean? When I look at FPGA manager status in Linux, it prints the following. root@cyclone5:~# cat /sys/class/fpga_manager/fpga0/state write init3.6KViews0likes5CommentsRe: Programming CycloneV FPGA from U-Boot SPL
Firstly, should that FPGA programming message come up with the default version of uboot on github right now? Does the bsp-create-settings command grab the rbf and build it into u-boot with commands to program the FPGA or does this need to be added manually? How do you partition and pack your files on to the SD card? Do you need to point u-boot to your script or will it begin running it automatically? I was using this script https://raw.githubusercontent.com/rsarwar87/altera-soc-rootfs/master/make_sdimage2.py to simplify the partitioning/formatting process. This script will only let you make 4 partitions it seems each with only one file per partition. Is there a way to combine the u-boot-with-spl.sfp with the uboot.scr into one binary? Thanks,3.7KViews1like0CommentsProgramming CycloneV FPGA from U-Boot SPL
I have a DE1-SoC board from Terasic. I am trying to boot a Linux kernel that can talk to the hardware in the FPGA portion. I am trying to verify that my FPGA is programmed during the boot cycle. I am currently following this workflow. https://rocketboards.org/foswiki/Documentation/BuildingBootloader My bootlogs show no indication that the FPGA is being programmed by the preloader before the kernel is decompressed and started. U-Boot SPL 2019.04-00246-g0c3e6f623d-dirty (Dec 20 2019 - 22:19:44 -0500) Trying to boot from MMC1 U-Boot 2019.04-00246-g0c3e6f623d-dirty (Dec 20 2019 - 22:19:44 -0500) CPU: Altera SoCFPGA Platform FPGA: Altera Cyclone V, SE/A5 or SX/C5 or ST/D5, version 0x0 BOOT: SD/MMC Internal Transceiver (3.0V) Watchdog enabled DRAM: 1 GiB MMC: dwmmc0@ff704000: 0 Loading Environment from MMC... *** Warning - bad CRC, using default environment In: serial Out: serial Err: serial Model: Altera SOCFPGA Cyclone V SoC Development Kit Net: Warning: ethernet@ff702000 (eth0) using random MAC address - a2:77:81:44:49:7a eth0: ethernet@ff702000 Hit any key to stop autoboot: 0 switch to partitions #0, OK mmc0 is current device Scanning mmc 0:1... Found /extlinux/extlinux.conf Retrieving file: /extlinux/extlinux.conf 157 bytes read in 1 ms (153.3 KiB/s) 1: Linux Default Retrieving file: /extlinux/../zImage 4700440 bytes read in 241 ms (18.6 MiB/s) append: root=/dev/mmcblk0p2 rw rootwait earlyprintk console=ttyS0,115200n8 Retrieving file: /extlinux/../socfpga_cyclone5_socdk.dtb 28016 bytes read in 3 ms (8.9 MiB/s) ## Flattened Device Tree blob at 02000000 Booting using the fdt blob at 0x2000000 Loading Device Tree to 03ff6000, end 03fffd6f ... OK Starting kernel ... When I start readinng fpga_manager sysfs files, they suggest the FPGA is not powered on root@cyclone5:~# cat /sys/class/fpga_manager/fpga0/state power off Does anyone know how to verify that the FPGA is programmed by the bootloader and if not, then how to program it with the bootloader4KViews0likes6Comments