Gyud0
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Re: SDRAM Controller FPGA IP- read x"FFFF" from the IP and not the ejected data from SDRAM
Hey, My answers: Which SDRAM Controller IP that you are using? SDRAM Controller Intel FPGA IP Which Quartus version and edition that you are using? Quartus 20.1 Prime Which device that you are working on? Cyclone V Are you using Intel Dev Kit or your own custom board? A custom board Are you using an example design or your own design? No Any memory datasheet and user guide that you are referring to? Yep, I'm using the MT48LC16M16A2:https://www.micron.com/-/media/client/global/Documents/Products/Data%20Sheet/DRAM/256Mb_sdr.pdf I'm repeating again that I see that the SDRAM eject the correct data via it's Address and data port (that connected to the FPGA- Via SignalTap), but the data that I got from the IP equales to x"FFFF" synchronized to avmm_readdatavalid pulse.SDRAM Controller FPGA IP- read x"FFFF" from the IP and not the ejected data from SDRAM
Hey, I'm using the SDRAM Controller Intel FPGA IP for a 256Mbits device (16 bit). When I execute a read operation via the Avalon MM interface, I see that the SDRAM eject the correct data via it's Address and data port (that connected to the FPGA), but the data that I got from the IP equales to x"FFFF" synchronized to avmm_readdatavalid pulse. Can you help me with this problem? ThanksConfiguration process error in Cyclone V
Hey, I have a FPGA Cyclone V device. When I convert the .sof file to a .jic file with Active serial x1 (and burn the new .jic file), the FPGA loaded unsuccessfully. when I'm waiting a few minutes between tries, the FPGA loaded successfully. In the other hand, when I convert the .sof file to a .jic file with Active serial x4 (and burn the new .jic file), the FPGA loaded successfully every try. Can you help me with this issue? Thank youRe: Generic serial Flash interface sector erase problem
My code in C: int main() { IOWR(INTEL_GENERIC_SERIAL_FLASH_INTERFACE_TOP_0_AVL_CSR_BASE,0x7,0x00000006); --Write enable IOWR(INTEL_GENERIC_SERIAL_FLASH_INTERFACE_TOP_0_AVL_CSR_BASE,0x8,0x00000001); --Write enable IOWR(INTEL_GENERIC_SERIAL_FLASH_INTERFACE_TOP_0_AVL_CSR_BASE,0xA,1); --Write enable IOWR(INTEL_GENERIC_SERIAL_FLASH_INTERFACE_TOP_0_AVL_CSR_BASE,0x7,0x000004DC); --Erase sector IOWR(INTEL_GENERIC_SERIAL_FLASH_INTERFACE_TOP_0_AVL_CSR_BASE,0x9,0x00010000); --Erase sector IOWR(INTEL_GENERIC_SERIAL_FLASH_INTERFACE_TOP_0_AVL_CSR_BASE,0x8,0x00000001); --Erase sector }Generic serial Flash interface sector erase problem
Hey, I'm using the Reference design Generic Serial Flash Interface IP on Quartus Prime 18.1 to access Micron MT25QL512Mb flash memory. Via NIOS processor, I able to erase the memory sector 0 (at address 0x00000000) data correctly in the 4-Byte address mode by the function: void erase_sector_micron() { IOWR(INTEL_GENERIC_SERIAL_FLASH_INTERFACE_TOP_0_AVL_CSR_BASE,0x7,0x000004DC); IOWR(INTEL_GENERIC_SERIAL_FLASH_INTERFACE_TOP_0_AVL_CSR_BASE,0x9,0x00000000); IOWR(INTEL_GENERIC_SERIAL_FLASH_INTERFACE_TOP_0_AVL_CSR_BASE,0x8,0x1); } But when I try to erase another sector, like sector 1, I don't see the erasing actually happens: void erase_sector_micron() { IOWR(INTEL_GENERIC_SERIAL_FLASH_INTERFACE_TOP_0_AVL_CSR_BASE,0x7,0x000004DC); IOWR(INTEL_GENERIC_SERIAL_FLASH_INTERFACE_TOP_0_AVL_CSR_BASE,0x9,0x00010000); IOWR(INTEL_GENERIC_SERIAL_FLASH_INTERFACE_TOP_0_AVL_CSR_BASE,0x8,0x1); } The sector 1 address is 0x10000 according to page 19 in the Datasheet: https://media-www.micron.com/-/media/client/global/documents/products/data-sheet/nor-flash/serial-nor/mt25q/die-rev-b/mt25q_qlkt_l_512_abb_0.pdf?rev=0ef0faa5f7b645d7bc11c30bfd27505b I would like to get some help here, Thanks
